1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device in which memory cells include capacitors, and in particular to a dynamic semiconductor memory device of a non-boosted word line type.
2. Description of the Background Art
FIG. 65 shows a structure of a main portion of a conventional dynamic semiconductor memory device, which will be referred to as a DRAM (dynamic random access memory). The structure of the conventional DRAM shown in FIG. 65 is disclosed by Fujishima et al, "A Storage-Node-Boosted RAM with Word Line Delay Compensation", 1982 IEEE International Solid-State Circuits Conference, pp. 66-67, for example.
FIG. 65 shows a structure related to one word line WL. Bit lines BL0-BLn are arranged in a direction crossing word line WL, and memory cells MC0-MCn are arranged corresponding to the crossings between word line WL and bit lines BL0-BLn . Each of memory cells MC0-MCn includes a capacitor CM for storing information and an access transistor MQ formed of an n-channel MOS transistor and turned on in response to a signal potential on word line WL connect one electrode (i.e., storage node) of capacitor CM to the corresponding one of bit lines BL0-BLn . In each of memory cells MC0-MCn, the other electrode (cell plate electrode node) of capacitor CM is connected to a common cell plate line CPL. Cell plate line CPL is connected to only the cell plate electrode nodes of capacitors CM of memory cells MC0-MCn connected to word line WL.
For adjusting the voltage level on cell plate line CPL, there is arranged a cell plate controller CVC which selectively controls a voltage Vg on cell plate line CPL in response to the signal potential on word line WL. Cell plate controller CVC includes a decoupling n-channel MOS transistor Q1 which receives on its gate a power supply voltage VDD, an n-channel MOS transistor Q2 which transmits power supply voltage VDD onto cell plate line CPL in response to activation of a precharge signal .phi.P, and an n-channel MOS transistor Q3 which has a gate coupled to word line WL through MOS transistor Q1 and transmits a control signal .phi.G onto cell plate line CPL.
When control signal .phi.G rises to H-level and the gate potential of MOS transistor Q3 is raised by a self-boot strap effect, MOS transistor Q1 for decoupling prevents transmission of the voltage thus raised onto word line WL.
Word line WL is provided at its other end with a word line driver WDR for driving word line WL to a selected state at the power supply voltage VDD level in accordance with an address signal (not shown). Bit lines BL0-BLn are precharged to the power supply voltage VDD level. The cell plate controller CVC is provided for each word line, and controls only cell plate voltages Vg of the memory cells connected to the selected word line. An operation of the DRAM shown in FIG. 65 will now be described below with reference to a timing chart of FIG. 66.
In a standby cycle before time Ta, word line WL is at L-level (ground voltage level) and in the unselected state. Precharge instructing signal .phi.P is at H-level, and MOS transistor Q2 in cell plate controller CVC is on so that cell plate voltage Vg on cell plate line CPL is at power supply voltage VDD level. Control signal .phi.G is at H-level, but word line WL is at L-level of ground voltage level so that MOS transistor Q3 is off.
At time Ta, an active cycle starts in response to activation (i.e., L-level) of a row address strobe signal /RAS (not shown). In this active cycle, signal .phi.G falls to L-level, and precharge instruction signal .phi.P also falls to L-level. Thereby, MOS transistor Q2 is turned off. Then, word line driver WDR drives the word line arranged corresponding to the addressed row to the selected state in accordance with the address signal. If word line WL is selected, word line driver WDR drives word line WL to H-level of power supply voltage VDD level. Thereby, access transistors MQ in memory cells MC0-MCn are turned on to couple memory cell capacitors CM to corresponding bit lines BL0-BLn , respectively. In response to rising of the potential on word line WL, MOS transistor Q3 is turned on so that cell plate voltage Vg on cell plate line CPL lowers to the ground voltage level (signal .phi.G is at L-level). As a result of this falling of cell plate voltage Vg, the potential on storage node of each memory cell capacitor CM is lowered by the capacitive coupling, and all charges accumulated in capacitor CM are transmitted onto corresponding one of bit lines BL0-BLn . In this manner, all the accumulated charges in each memory cell capacitor CM are transmitted onto corresponding one of bit lines BL0-BLn in response to the falling of cell plate voltage Vg, whereby the memory cell data is rapidly read onto corresponding one of bit lines BL0-BLn without an influence of delay in signal transmission on word line WL.
Then, sense amplifiers (not shown) operate to sense, amplify and latch the memory cell data. The potential on the bit line onto which the data at H-level is read attains power supply voltage VDD level, and the potential on the bit line onto which the data at L-level is read attains ground voltage VSS level at time Tc. The potential on the storage node (i.e., the electrode connected to the access transistor) of the capacitor of the memory cell storing H-level attains the voltage level of (VDD-VT) due to threshold voltage loss of access transistor MQ, where VT represents a threshold voltage of access transistor MQ.
Then, data is written into or read from the selected memory cell, and one memory cycle is completed. This completion of the memory cycle is implemented, e.g., by rising of row address strobe signal /RAS. In this operation, control signal .phi.G first rises to H-level at time Td. Word line WL is at power supply voltage VDD level, and control signal .phi.G is transmitted onto cell plate line CPL via MOS transistor Q3. When the voltage level of control signal .phi.G rises, MOS transistor Q3 has its gate potential boosted to a voltage level higher than power supply voltage VDD through the self-boot strap effect, and MOS transistor Q3 transmits control signal .phi.G at power supply voltage VDD level onto cell plate line CPL.
In response to rising of control signal .phi.G, cell plate voltage Vg rises to power supply voltage VDD level. When cell plate voltage Vg rises from the ground voltage level to the power supply voltage level, capacitive coupling in capacitors CM of memory cells MC0-MCn raises the voltage levels on their storage nodes. In the memory cell storing H-level data, the voltage level on the storage node of the capacitor further rises from the level of (VDD-VT) by .alpha..multidot.VDD, where .alpha. represents a coefficient of capacitive coupling. Word line WL is at power supply voltage VDD level, and the bit line connecting to the memory cell storing the H-level data likewise has the potential at power supply voltage VDD level. Therefore, access transistor MQ is turned off in accordance with the rising of voltage on the storage node caused by this capacitive coupling, and the storage node of the capacitor of the memory cell storing H-level data is raised to and held at a voltage level higher than power supply voltage VDD.
In the memory cells storing L-level data, the potentials on the storage nodes of the capacitors likewise rise. However, the sense amplifiers clamp the potentials on the bit lines for these memory cells, respectively. Therefore, the potential rising of these storage nodes are clamped by the corresponding sense amplifiers to the ground voltage level, respectively. Then, word line WL is driven to the unselected state, and subsequently precharge instructing signal .phi.P attains H-level so that cell plate voltage Vg on cell plate line CPL is held at power supply voltage VDD level.
In the standby cycle (precharged state) at time Te, cell plate voltage Vg is held at the power supply voltage level, and the storage node of the memory cell storing H-level data is at the voltage level higher than power supply voltage VDD.
When word line WL is unselected, word line WL is at the ground voltage level, and MOS transistor Q3 maintains the off state. Even when control signal .phi.G rises to H-level, MOS transistor Q1 maintains the on state so that the gate potential of MOS transistor Q3 is held at the ground voltage level by word line driver WDR, and cell plate voltage Vg is held at the power supply voltage VDD level. Therefore, the amount of charges accumulated in the memory cell do not change.
BY using the control signal as described above, the data at the voltage level higher than power supply voltage VDD can be held without setting the voltage level on the selected word line WL to a level higher than power supply voltage VDD. Therefore, it is not necessary to raise the voltage level on the word line WL to a level higher than power supply voltage VDD, and it is possible to prevent failure of the word lines and breakdown of the gate insulating films of the access transistors.
Such a case will now be considered that, in FIG. 65, word line WL is in the unselected state, and the cell plate controller CVC is operated. It is also assumed that the memory cell has stored data at L-level. Word line WL is in the unselected state and is at the ground voltage level. In this state, cell plate controller CVC lowers cell plate voltage Vg from power supply voltage VDD level to the ground voltage level. In this operation, as shown in FIG. 67, the capacitive coupling of the capacitor of the memory cell storing L-level data lowers the voltage level on storage node SN from the ground voltage level to a negative voltage level. Although word line WL is at the ground voltage level, storage node SN is at the negative voltage level, and the access transistor MQ is turned on so that charges flow from the corresponding bit line to this storage node at the negative voltage level, and the voltage level on storage node SN rises.
When the word line is selected, the sense amplifier does not yet operate so that the bit line is in the electrically floating state, and the voltage level on the bit line lowers as a result of flow of the charges into the memory cell storing the L-level data. Therefore, if the selected memory cell stores the data at H-level, the level of the read voltage of this selected memory cell lowers. This reduces a difference in voltage level between the H-level data and the L-level data upon operation of the sense amplifier, and therefore the sensing operation cannot be performed accurately. Even when cell plate voltage Vg is lowered after completion of the operation of the sense amplifier, the potential on the storage node likewise rises as a result of inflow of charges.
After the sensing operation is completed and reading/writing of data is completed, cell plate voltage Vg is raised from the ground voltage level to power supply voltage VDD level. As a result of this rising of voltage level on cell plate voltage Vg, the potential on storage node SN of the unselected memory cell is raised by the capacitive coupling. Therefore, the voltage level on storage node SN of the unselected memory cell which stores the L-level data rises, and the L-level data changes into the H-level data.
In this conventional word line non-boosting scheme, it is necessary to provide the cell plate controller corresponding to the respective word lines, and to isolate cell plate line CPL for each word line from those for the other word lines.
FIG. 68 schematically shows a structure of a DRAM cell in the prior art, and more specifically shows a cross sectional structure of memory cells of two bits.
In FIG. 68, P-type semiconductor substrate region 900 is provided at its surface with heavily doped N-type impurity regions 901a, 901b and 901c which are spaced from each other. Cell isolation insulating films 902a and 902b are formed around impurity regions 901a and 901c, respectively. A gate electrode layer 903a is arranged on a channel region between impurity regions 901a and 901b with a gate insulating film (not shown) thereunder. A gate electrode layer 903b is arranged on a channel region between impurity regions 901b and 901c with a gate insulating film (not shown) thereunder. Gate electrode layers 903c and 903d which form word lines connected to memory cells in other rows are arranged above cell isolation insulating films 902a and 902b, respectively. Impurity region 901b is connected to a conductive layer 904 forming a bit line. Conductive layer 904 is formed of, e.g., a first level aluminum interconnection layer, and is located at a layer higher than gate electrode layers 903a-903d forming the word lines.
A conductive layer 905a forming a storage node is connected to impurity region 901a, and a conductive layer 905b forming a storage node is connected to impurity region 901c. Each of conductive layers 905a and 905b has, for example, a T-shaped cross sectional structure, of which flat top portion is located above conductive layer 904 forming the bit line. Conductive layers 906 are faced to the top and side surfaces of conductive layers 905a and 905b. Conductive layer 906a and conductive layer 905a facing to each other form a memory cell capacitor. Conductive layer 906b and conductive layer 905b facing to each other form another memory cell capacitor.
As shown in FIG. 68, the capacitors are formed at a layer higher than gate electrode layers 903a-903c forming the word lines, whereby an area occupied by the capacitors in a plan view as well as the memory cell size are reduced, and the word line pitch is also reduced so that the degree of integration of the memory cells can be increased.
FIG. 69 shows a positional relationship between storage nodes of the memory cells and the word lines. FIG. 69 representatively shows four word lines WL0-WL3 and six memory cells. Bit lines BL and /BL are arranged perpendicularly to word lines WL0-WL3. Storage nodes SN0-SN5 of the memory cells have extended portions located above the corresponding word lines and the neighboring word lines, respectively. Each storage node is connected to the impurity region represented by a circle in FIG. 69. These storage nodes SN0-SN5 correspond to the conductive layer 905a or 905b in FIG. 68. The memory cells having storage nodes SN0 and SN1 are connected to bit line BL through a bit line contact BLC0.
The memory cells having storage nodes SN4 and SN5 are connected to bit line BL through a bit line contact BLC1. The memory cells having storage nodes SN2 and SN3 are connected to bit line /BL (not shown). Word line WL0 selects the memory cell having storage node SN2, and word line WL1 selects the memory cells having storage nodes SN0 and SN4. Word line WL2 selects the memory cells having storage nodes SN1 and SN5, and word line WL3 selects the memory cell having storage node SN3.
In the arrangement shown in FIG. 69, it is now assumed that the cell plate line for each row is to be isolated from those for the other rows. As shown in FIG. 69, the storage nodes are arranged along the direction of extension of the word lines. Therefore, it is impossible to employ such a structure that the electrode layer (906a, 906b) forming the cell plate node extends linearly in the row direction for each row. A cell plate line parallel with the word line may be arranged above the word line, and may be electrically connected to the cell plate nodes facing to the storage nodes. However, the word line is made of polycrystalline silicon and, usually, is electrically connected to an aluminum interconnection layer having a low resistance and formed at a higher level in a predetermined region (word line shunt region). The above arrangement of the cell plate lines parallel with word lines (WL0-WL3) complicates the layout of the cell plate lines in the word line shunt regions.
As another structure, the cell plate line may be disposed between the word lines, and may be electrically connected to the cell plate node serving as the capacitor electrode facing to the corresponding storage node. In this case, however, the cell plate line must have a larger line width than the word line for rapidly changing the cell plate voltage because the cell plate layer (906a, 906b) is made of polycrystalline silicon and has a large resistance value. Therefore, the condition on the pitch of the cell plate lines becomes extremely severe if the wide cell plate lines are to be arranged between the submicronized word lines. This results in problems such as increase in parasitic capacitance and defective insulation. Therefore, in the memory cell structure achieving a high density of, e.g., stacked capacitor cells as shown in FIG. 68, it is extremely difficult to divide the cell plate corresponding to the respective word lines.
If the word line is increased in length and connects an increased number of memory cells thereto, the cell plate lines divided corresponding to the word lines also increase in length, and the resistance thereof increases so that it is impossible to change rapidly the cell plate voltage, resulting in a problem that the times required for reading and writing data increase.
If the voltage level on the selected word line is to be raised to a level higher than the power supply voltage, it is necessary to increase the thickness of the gate insulating film of the memory cell transistor for ensuring intended breakdown voltage characteristics thereof. If a DRAM and a logic such as a processor are to be integrated on a common semiconductor chip, it is necessary that MOS transistors (insulated gate type field effect transistors) which are components of the logic have insulating films different in thickness from those of the memory cell transistors of the DRAM. In this case, therefore, the gate insulating films of the MOS transistors of the logic must be produced in manufacturing steps different from those of forming the gate insulating films of the memory cell transistors, resulting in increase in number of the manufacturing steps. If the peripheral transistor and the memory cell transistor have the gate insulating films of the same thickness, the operation speed of the peripheral transistor decreases.